Program

Monday, October 6th, 2025
6:00 PM – 8:00 PMConference Reception & Poster Session 🎉 – Hotel Lobby
Tuesday, October 7th, 2025
9:00 AM – 10:00 AMKeynote Address I
10:00 AM – 10:20 AMCoffee Break ☕
10:20 AM – 12:00 PMSession 1: The CXL Ecosystem
10:20 AM – 10:40 AMRoberto Gioiosa – “Hardware-Software Co-Development for Emerging CXL Architectures”
10:40 AM – 11:00 AMAnusha Devulapally – “Revisiting Pebble Games for Modeling and Efficient Use of Disaggregated Memory Systems”
11:00 AM – 11:20 AMFnu Asad Ul Haq – “ZipCXL: CXL-based Main Memory Compression at Low Performance Penalty”
11:20 AM – 11:40 AMEllis Giles – “Hierarchical Framework for Multi-node Compute eXpress Link Memory Transactions”
11:40 AM – 12:00 PMChandrahas Tirumalasetty – “Exploring multi-level cache prefetching for fabric attached memory”
12:00 PM – 1:30 PMLunch Break & Poster Session 🥪
1:30 PM – 2:50 PMSession 2: Emerging Technologies and Reliability
1:30 PM – 1:50 PMLunkai Zhang – “ECC Replay: A Practical and Efficient Scheme To Tolerate High Stuck Bit Rate in Future Memories”
1:50 PM – 2:10 PMFaaiq Waqar – “CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms”
2:10 PM – 2:30 PMMohammad Rezaeifar – “A Neural Network Approach for Calibrating Memristor Crossbars”
2:30 PM – 2:50 PMSara Ameli – “Associative clustering with analog content-addressable memory”
2:50 PM – 3:10 PMCoffee Break ☕
3:10 PM – 4:30 PMSession 3: Optimizing DRAM: Controllers, Mapping, and Writes
3:10 PM – 3:30 PMDivyansh Maura – “Precision Aware Bank Separated Data Placement for Enhanced DRAM Performance in Mixed-Precision HPCWorkloads”
3:30 PM – 3:50 PMK Chitra – “Read latency hiding in DRAM using split write”
3:50 PM – 4:10 PMAndrei Rotaru – “A Mathematical Model for XOR-Based Application Specific DRAM Address Mapping Schemes”
4:10 PM – 4:30 PMAbdelrhman Abotaleb – “Stream-Aware Intelligent Memory Controller through HW/SW Co-Design”
4:30 PM – 4:50 PMCoffee Break ☕
4:50 PM – 6:05 PMSpecial Session: Memory Security 🔒
4:50 PM – 5:05 PMBruce Jacob – “Security Session: Extended Abstract: Some Security Aspects of the Memory System You Might Not Have Known”
5:05 PM – 5:20 PMWilliam Casey – “Security Session: Extended Abstract: Opportunities and Challenges: Hardware Vulnerability descriptions with Hybrid Logic.”
5:20 PM – 5:35 PMAvinash Srinivasan – “Security Session: Extended Abstract: Security and Forensics–Is Solid State Drive a Friend or a Foe?”
5:35 PM – 5:50 PMJennie Hill – “Security Session: Extended Abstract: A Side-channel Framework and Microarchitectural Analysis Application: Ransomware Detection with Hardware Performance Counters”
5:50 PM – 6:05 PMMehdi Elahi – “Security Session: Extended Abstract: On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures”
6:05 PM – 7:05 PMPanel: “Emerging Threats and Defenses in the Memory Hierarchy” Panelists: TBD (Session speakers and invited guests)
Wednesday, October 8th, 2025
9:00 AM – 10:00 AMKeynote Address II
10:00 AM – 10:20 AMCoffee Break ☕
10:20 AM – 11:40 AMSession 4: PIM & AI Accelerators
10:20 AM – 10:40 AMErsin Cukurtas – “IMPRINT: In-Memory Processing with Indirect Addressing Techniques for GPU-hosted HBM-PIM”
10:40 AM – 11:00 AMAlif Ahmed – “Late Breaking Results: TGN-PNM: A Near-Memory Architecture for Temporal GNN Inference on 3D-Stacked Memory”
11:00 AM – 11:20 AMMorteza Baradaran – “Late Breaking Results: TriPIM — Exact Triangle Counting on UPMEM PIM for Graph Analytics”
11:20 AM – 11:40 AMMd. Azahar Alam – “Scalable Analytical Memory Modeling of AI Accelerators”
11:40 AM – 1:10 PMLunch Break & Poster Session 🥪
1:10 PM – 2:30 PMSession 5: Performance Modeling and Analysis Frameworks
1:10 PM – 1:30 PMElias Perdomo – “Memory Sandbox 2.0: A Framework for Enabling HBM2e vs HBM2 Performance and Telemetry Analysis on Xilinx FPGAs”
1:30 PM – 1:50 PMDhruv Gajaria – “HOME: A Hierarchy-Oriented Memory Evaluation Framework for Fast Contention Analysis”
1:50 PM – 2:10 PMAbdur Razzak – “Compile-Time Estimation for Nested Loops Array Reuses”
2:10 PM – 2:30 PMGabin Schieffer – “A Deep Dive into Inter-APU Communication Efficiency on AMD MI300A Multi-APU Systems with Infinity Fabric Interconnect”
2:30 PM – 2:50 PMCoffee Break ☕
2:50 PM – 4:10 PMSession 6: Cache, Locality, and System Software
2:50 PM – 3:10 PMJ. Zach McMichael – “VMem: A Framework for Application Management of Physical Memory Resources”
3:10 PM – 3:30 PMHyunwoo Kim – “Secure IVSHMEM: End-to-End Shared-Memory Protocol with Hypervisor-CA Handshake and In-Kernel Access Control”
3:30 PM – 3:50 PMYanghui Wu – “Eviction Policy Optimization in Lease Caches”
3:50 PM – 4:10 PMFangzhou Liu – “Data Access Complexity: Monotonicity and Proportionality”
4:10 PM – 4:30 PMCoffee Break ☕
4:30 PM – 6:00 PMPanel: Topic: “Memory Systems in the Age of AI: Challenges and Opportunities” Panelists: TBD
6:00 PMAwards & Conference Closing Remarks 🏆👋