Conference Organizers

  • Bruce Jacob, U. Maryland
  • Kathy Smiley, Memory Systems
  • Rajat Agarwal, Intel
  • Ameen Akel, Micron
  • James Ang, Sandia National Labs
  • Bruce Childers, U. Pittsburgh
  • Zeshan Chishti, Intel
  • Bruce Christenson, Intel
  • Chen Ding, U. Rochester
  • David Donofrio, Berkeley Lab
  • Wendy Elsasser, ARM
  • Maya Gokhale, LLNL
  • Xiaochen Guo, Lehigh U.
  • Michael Ignatowski, AMD
  • Matthias Jung, U. Kaiserslautern
  • Hyesoon Kim, Georgia Tech
  • Scott Lloyd, LLNL
  • Sally A. McKee, Chalmers/Rambus
  • Moinuddin Qureshi, Georgia Tech
  • David Resnick, Sandia National Labs
  • Arun Rodrigues, Sandia National Labs
  • Robert Voigt, Northrop Grumman
  • Vincent Weaver, U. Maine
  • Christian Weis, U. Kaiserslautern
  • Kenneth Wright, Rambus
  • Sudhakar Yalamanchili, Georgia Tech
  • Ke Zhang, Chinese Acad. of Sciences
  • Jishen Zhao, UC Santa Cruz

Conference Program

Mon Oct 2 Welcome Reception 5:00 – 9:00 pm

Tue Oct 3 Breakfast 7:45 am

8:35 am Opening Remarks

8:40 am Software Keynote: Peter Kogge 
 Dept. of Computer Science and Engineering
 University of Notre Dame

9:40 am Break

10:00 am Session 1: Processing In and or Near Memory

Session Chair: Mike Ignatowski, AMD

10:00 am AIM: Accelerating Computational Genomics through Scalable 
and Noninvasive Accelerator-Interposed Memory p.3

Jason Cong (UCLA), Zhenman Fang (UCLA), Michael Gill (UCLA), Farnoosh Javadi (UCLA), Glenn Reinman (UCLA)

10:20 am PHOENIX: Efficient Computation in Memory p.15

Mats Rimborg (Chalmers University of Technology), Pedro Trancoso (University of Cyprus), Gunnar Carlstedt (Chalmers University of Technology)

10:40 am Near Memory Key/Value Lookup Acceleration p.26

Scott Lloyd (LLNL), Maya Gokhale (LLNL)

11:00 am The Sparse Data Reduction Engine: Chopping Sparse Data One Byte at a Time p.34

Jonathan Beard (Arm Research)

11:20 am Lightweight SIMT Core Designs for Intelligent 3D Stacked DRAM p.49

Chad Kersey (Georgia Institute of Technology), Sudhakar Yalamanchili (Georgia Institute of Technology), Hyesoon Kim (Georgia Institute of Technology College of Computing)

11:40 am Identifying the Potential of Near Data Processing for Apache Spark p.60

Ahsan Javed Awan (KTH Royal Institute of Technology), Eduard Ayguade (Technical University of Catalunya and Barcelona Super Computing Center), Kazuaki Ishizaki (IBM Research – Tokyo), Vladimir Vlassov (KTH Royal Institute of Technology), Mats Brorsson (KTH Royal Institute of Technology), Moriyoshi Ohara (IBM Research)

12:00 pm Conference Lunch

1:00 pm Session 2: DRAM Technologies

Session Chair: Sally McKee, Rambus

1:00 pm A Bandwidth Accurate, Flexible and Rapid Simulating Multi-HMC Modeling Tool p.71

Patrick Siegl (TU Braunschweig, Abteilung Technische Informatik, E.I.S.), Rainer Buchty (TU Braunschweig, Abteilung Technische Informatik, E.I.S.), Mladen Berekovic (TU Braunschweig, Abteilung Technische Informatik, E.I.S.)

1:20 pm CramSim: Controller and Memory Simulator p.83

Michael Healy (IBM T.J. Watson Research Center), Seokin Hong (IBM T.J. Watson Research Center)

1:40 pm Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact p.86

Radhika Jagtap (Arm Ltd.), Matthias Jung (Fraunhofer IESE), Wendy Elsasser (Arm Inc.), Christian Weis (University of Kaiserslautern), Andreas Hansson (Arm Ltd.), Norbert Wehn (University of Kaiserslautern)

2:00 pm Odd-ECC: On-Demand DRAM Error Correcting Codes p.96

Alirad Malek (Chalmers Univeristy), Evangelos Vasilakis (Chalmers univeristy), Vassilis Papaefstathiou (FORTH-ICS), Pedro Trancoso (Chalmers univeristy), Ioannis Sourdis (Chalmers university)

2:20 pm Evaluating Hybrid Memory Cube Infrastructure To Support High-Performance 
Sparse Algorithms p.112

Kartikay Garg (Georgia Institute of Technology), Jeffrey Young (Georgia Institute of Technology)

2:40 pm Using Run-Time Reverse-Engineering to Optimize DRAM Refresh p.115

Deepak M. Mathew (University of Kaiserslautern), Éder F. Zulian (University of Kaiserslautern), Matthias Jung (Fraunhofer IESE), Kira Kraft (University of Kaiserslautern), Christian Weis (University of Kaiserslautern), Bruce Jacob (University of Maryland), Norbert Wehn (University of Kaiserslautern)

3:00 pm Break

3:20 pm Session 3: Caches and Data Management

Session Chair: Chen Ding, University of Rochester

3:20 pm A Study of Unnecessary Write Backs p.127

Chris Garman (Lehigh University), Xiaochen Guo (Lehigh University), Michael Spear (Lehigh University)

3:40 pm SprBlk Cache: Enabling Fault Resilience at Low Voltages p.130

Nafiul Siddique (New Mexico State University), Abdel-Hameed Badawy (New Mexico State University)

4:00 pm Efficient STT-RAM Last-Level-Cache Architecture to Replace DRAM Cache p.141

Fazal Hameed (Chair for Compiler Construction, Computer Science Department, TU-Dresden), Christian Menard (Chair for Compiler Construction, Computer Science Department, TU-Dresden), Jeronimo Castrillon (Chair for Compiler Construction, Computer Science Department, TU-Dresden)

4:20 pm LMStr: Exploring Shared Hardware Controlled Scratchpad Memory for Multicores p.152

Nafiul Siddique (New Mexico State University), Abdel-Hameed Badawy (New Mexico State University), Dave Resnick (Sandia National Laboratory), Jeanine Cook (Sandia National Laboratories)

4:40 pm Probabilistic Replacement Strategies for Improving the Lifetimes of NVM-Based Caches p.166

Elizabeth Reed (University of Illinois), Alaa Alameldeen (Intel), Helia Naeimi (Intel), Patrick Stolt (Intel)

5:00 pm Logging in Persistent Memory: to Cache, or Not to Cache? p.177

Mengjie Li (UC Santa Cruz), Matheus Ogleari (UC Santa Cruz), Jishen Zhao (UC Santa Cruz)

5:20 pm Break

5:40 – 7:30 pm Spirited Discussion

Memory Systems Problems and Solutions

  • Chen Ding, University of Rochester
  • David Donofrio, Berkeley Labs
  • Scott Lloyd, LLNL
  • Dave Resnick, Sandia
  • Uzi Vishkin, University of Maryland

7:45 pm Dinner — Regular attendees on your own 
 Program Committee dinner meeting — A La Lucia, Alexandria

Wed Oct 4 Breakfast 7:45 am

8:40 am Hardware Keynote: David T. Wang 
 Director of Memory Product Planning

9:40 am Break

10:00 am Session 4: Next-Generation Memory Technology Details

Session Chair: Robert Voigt, Northrop Grumman

10:00 am Do Superconducting Processors Really Need Cryogenic Memories? 
The Case for Cold DRAM p.183

Fred Ware (Rambus), Liji Gopalakrishnan (Rambus), Eric Linstadt (Rambus), Sally A. McKee (Rambus), Thomas Vogelsang (Rambus), Kenneth L. Wright (Rambus), Craig Hampel (Rambus), Gary Bronner (Rambus)

10:20 am Cryogenic-DRAM Based Memory System for Scalable Quantum Computers: 
A Feasibility Study p.189

Swamit Tannu (Georgia Institute of Technology), Douglas Carmean (Microsoft), Moinuddin Qureshi (Georgia Institute of Technology)

10:40 am Memory Reliability for Cells with Strong Bit-Coupling Interference p.196

Kfir Mizrachi (Technion, Israel Institute of Technology), Ilan Bloom (Technion, Israel Institute of Technology), Yuval Cassuto (Technion, Israel Institute of Technology)

11:00 am Mitigating Bitline Crosstalk Noise in DRAM Memories p.205

Seyed Mohammad Seyedzadeh (University of Pittsburgh), Donald Edward Kline Jr (University of Pittsburgh), Alex K Jones (University of Pittsburgh), Rami Melhem (University of Pittsburgh)

11:20 am Memristive Voltage Divider: A Bipolar ReRAM-Based Unit for Non-Volatile Flip-Flops p.217

Mehrdad Biglari (Friedrich-Alexander University Erlangen-Nürnberg (FAU)), Dietmar Fey (Friedrich-Alexander University Erlangen-Nürnberg (FAU))

11:40 am Thermal-Aware, Heterogeneous Materials for Improved Energy and Reliability 
in 3D PCM Architectures p.223

Heba Saadeldeen (Intel Corporation), Zhaoxia Deng (University of California, Santa Barbara), Timothy Sherwood (University of California, Santa Barbara), Fred Chong (University of Chicago)

12:00 pm Conference Lunch

1:00 pm Session 5: Software and Hardware Optimization Techniques

Session Chair: Scott Lloyd, LLNL

1:00 pm Memory Equalizer for Lateral Management of Heterogeneous Memory p.239

Chen Ding (University of Rochester), Chencheng Ye (Huazhong University of Science and Technology), Hai Jin (Huazhong University of Science and Technology)

The Interaction of Last-Level-Cache Mechanisms on Modern Processors p.249

Rakhi Hemani (IIITD), Subhasis Banerjee (IBM), Apala Guha (Indraprastha Institute of Technology)

1:20 pm CoMerge: Toward Efficient Data Placement in Shared Heterogeneous Memory Systems p.251

Thaleia Dimitra Doudali (Georgia Institute of Technology), Ada Gavrilovska (Georgia Institute of Technology)

1:40 pm mpibind: A Memory-Centric Mapping of Hybrid Applications onto Emerging Systems p.262

Edgar A Leon (Lawrence Livermore National Laboratory)

2:00 pm DRAM-Related Challenges in Task Scheduling with Timing Predictability 
on COTS Multi-Cores for Safety-Critical Systems p.265

Ankit Agrawal (Technische Universität Kaiserslautern), Gerhard Fohler (Technische Universität Kaiserslautern)

2:20 pm BATMAN: Techniques for Maximizing System Bandwidth of Memory Systems 
with Stacked DRAM p.268

Chiachen Chou (Georgia Institute of Technology), Aamer Jaleel (NVIDIA), Moinuddin Qureshi (Georgia Institute of Technology)

2:40 pm Break

3:00 pm Session 6: Thinking Outside the Box

Session Chair: Kenneth Wright, Rambus

3:00 pm Enabling a Reliable STT-MRAM Main Memory Simulation p.283

Kazi Asifuzzaman (Barcelona Supercomputing Center), Rommel Sanchez Verdejo (Barcelona Supercomputing Center), Petar Radojkovic (Barcelona Supercomputing Center)

3:20 pm PageVault – Securing Off-Chip Memory using Page-based Authentication p.293

Blaise Tine (Georgia Institute of Technology), Sudhakar Yalamanchili (Georgia Institute of Technology)

3:40 pm Long Short Term Memory Based Hardware Prefetcher p.305

Yuan Zeng (Lehigh University), Xiaochen Guo (Lehigh University)

4:00 pm Task Replication and Control for Highly Parallel In-Memory Stores p.312

Fernando Martin Del Campo (University of Toronto), Paul Chow (University of Toronto)

4:20 pm DyAdHyTM: A Low Overhead Dynamically Adaptive Hybrid Transactional Memory 
with Application to Large Graphs p.327

Mohammad Qayum (New Mexico State University), Abdel-Hameed Badawy (New Mexico State University), Jeanine Cook (Sandia National Lab)

4:40 pm Rock: A Framework for Pruning the Design Space of Hybrid Main Memory Systems p.337

Dmitry Knyaginin (Chalmers University of Technology), Per Stenstrom (Chalmers University of Technology)

5:00 pm Break

5:20 – 7:20 pm Spirited Discussion

New and Cool Memory Technologies

  • Jonathan Beard, Arm
  • Zeshan Chishti, Intel
  • Mike Ignatowski, AMD
  • Robert Voigt, Northrop Grumman

7:30 pm Conference Dinner, Awards, … and … Murder?

Thu Oct 5 Breakfast 7:15 am

8:40 am Systems Keynote: Phil Emma 
 Chief Scientist (recently retired)

9:40 am Break

10:00 am Session 7: Management of Non-Volatile Memories

Session Chair: David Donofrio, Berkeley Labs

10:00 am NEMO: An Energy-Efficient Hybrid Main Memory System for Mobile Devices p.351

Bahareh Pourshirazi (University of Illinois at Chicago), Zhichun Zhu (University of Illinois at Chicago)

10:20 am Composing Lifetime Enhancing Techniques for Non-Volatile Main Memories p.363

Andres Amaya Garcia (Arm Ltd.), William Wang (Arm Ltd.), Rene de Jong (Arm Ltd.), Stephan Diestelhorst (Arm Ltd.)

10:40 am Improving SSD Lifetime with Byte-Addressable Metadata p.374

Yanqin Jin (University of California, San Diego), Hung-Wei Tseng (North Carolina State University), Yannis Papakonstantinou (University of California, San Diego), Steven Swanson (University of California, San Diego)

11:00 am REMAP: A Reliability/Endurance Mechanism for Advancing PCM p.385

Mohammad Khavari Tavana (Northeastern University), Amir Kavyan Ziabari (Northeastern University), Mohammad Arjomand (Pennsylvania State University), Mahmut Kandemir (Pennsylvania State University), Chita Das (Pennsylvania State University), David Kaeli (Northeastern University)

11:20 am Speculative Paging for Future NVM and SSD p.399

Viacheslav Fedorov (Texas A&M University), Jinchun Kim (Texas A&M University), Mian Qin (Texas A&M University), A. L. Narasimha Reddy (Texas A&M University), Paul Gratz (Texas A&M University)

11:40 am Performance Analysis for Using Non-Volatile Memory DIMMs: 
Opportunities and Challenges p.411

Amro Awad (Sandia National Laboratories), Simon Hammond (Sandia National Laboratories), Clay Hughes (Sandia National Laboratories), Arun Rodrigues (Sandia National Laboratories), Scott Hemmert (Sandia National Laboratories), Robert Hoekstra (Sandia National Laboratories)

12:00 pm Closing Remarks