Conference Organizers

  • Bruce Jacob, U. Maryland
  • Kathy Smiley, Memory Systems, LLCR
  • Rajat Agarwal, Intel
  • Abdel-Hameed Badawy, NMSU Jonathan Beard, Arm
  • Ishwar Bhati, Intel
  • Bruce Christenson, Intel
  • Zeshan Chishti, Intel 
  • Zhaoxia (Summer) Deng, Facebook Chen Ding, U. Rochester
  • David Donofrio, Berkeley Lab Dietmar Fey, FAU Erlangen-Nürnberg Maya Gokhale, LLNL
  • Xiaochen Guo, Lehigh U.
  • Manish Gupta, NVIDIA
  • Fazal Hameed, TU Dresden
  • Matthias Jung, Fraunhofer IESE
  • Kurt Keville, MIT
  • Hyesoon Kim, Georgia Tech
  • Scott Lloyd, LLNL
  • Sally A. McKee, Clemson
  • Moinuddin Qureshi, Georgia Tech Petar Radojkovic, BSC
  • Arun Rodrigues, Sandia National Labs Robert Voigt, Northrop Grumman Gwendolyn Voskuilen, Sandia
  • David T. Wang, Samsung
  • Vincent Weaver, U. Maine
  • Norbert Wehn, U. Kaiserslautern Yuan Xie, UC Santa Barbara
  • Ke Zhang, Chinese Acad. of Sciences Xiaodong Zhang, Ohio State
  • Jishen Zhao, UC San Diego

Conference Program

Mon Oct 1 Welcome Reception 5:00 – 9:00 pm
Maryland Ballroom A, Foyer

Tue Oct 2 Breakfast Maryland Ballroom 1&2 8:00 am

Tuesday Meeting: Maryland Ballroom A

8:50 am Opening Remarks

9:00 am Software Keynote: Brian Barrett
Principal Engineer
Amazon Web Services,

10:00 am Break

10:20 am Session 1: Datacenters and Large Memories p.1

Session Chair: Matthias Jung, Fraunhofer IESE

10:20 am Design Guidelines for High-Performance SCM Hierarchies p.3

Dmitrii Ustiugov (EcoCloud, EPFL), Alexandros Daglis (EcoCloud, EPFL), Javier Picorel (Huawei), Mark Sutherland (EcoCloud, EPFL), Edouard Bugnion (EcoCloud, EPFL), Babak Falsafi (EcoCloud, EPFL), Dionisios Pnevmatikatos (FORTH-ICS & ECE-TUC)

10:40 am A Comprehensive Memory Analysis of Data Intensive Workloads
on Server Class Architecture p.19

Hosein Mohammadi Makrani (George Mason University), Hossein Sayadi (George Mason University), Sai Manoj Pudukotai Dinakarra (George Mason University), Setareh Rafatirad (George Mason University), Houman Homayoun (George Mason University)

11:00 am HUB: Hugepage Ballooning in Kernel-Based Virtual Machines p.31

Jingyuan Hu (Peking University), Xiaokuang Bai (Peking University), Sai Sha (Peking University), Yingwei Luo (Peking University), Xiaolin Wang (Peking University), Zhenlin Wang (Michigan Technological University)

11:20 am Memory Failure Prediction Using Online Learning p.38

Xiaoming Du (Intel), Cong Li (Intel)

11:40 am Quantify the Performance Overheads of PMDK p.50

William Wang (Arm Research), Stephan Diestelhorst (Arm Research)

12:00 pm Conference Lunch Maryland Ballroom 1&2
… and Group Picture

1:00 pm Session 2: Memory for Parallel Systems & Architectures I p.53

Session Chair: Scott Lloyd, Lawrence Livermore National Lab

1:00 pm A Load Balancing Technique for Memory Channels p.55

Byoungchan Oh (University of Michigan), Nam Sung Kim (University of Illinois at Urbana-Champaign), Jeongseob Ahn (Ajou University), Bingchao Li (Civil Aviation University of China), Ronald Dreslinski (University of Michigan), Trevor Mudge (University of Michigan)

1:20 pm Cooperative NV-NUMA: Prolonging Non-Volatile Memory Lifetime through Bandwidth Sharing p.67

Mohammad Reza Jokar (University of Chicago), Lunkai Zhang (University of Chicago), Frederic Chong (University of Chicago)

1:40 pm GraphIA: An In-situ Accelerator for Large-scale Graph Processing p.79

Gushu Li (University of California, Santa Barbara), Guohao Dai (Tsinghua University), Shuangchen Li (University of California, Santa Barbara), Yu Wang (Tsinghua University), Yuan Xie (University of California, Santa Barbara)

2:00 pm Dynamic Fine-Grained Sparse Memory Accesses p.85

Berkin Akin (Intel), Chiachen Chou (Google), Jongsoo Park (Facebook), Christopher Hughes (Intel), Rajat Agarwal (Intel)

2:20 pm Memory-System Design Challenges in Realizing Monolithic Computers p.98

Meenatchi Jagasivamani (University of Maryland), Candace Walden (University of Maryland), Devesh Singh (University of Maryland), Luyi Kang (University of Maryland), Shang Li (University of Maryland), Mehdi Asnaashari (Crossbar Inc.), Sylvain Dubois (Crossbar Inc.), Bruce Jacob (University of Maryland), Donald Yeung (University of Maryland)

2:40 pm Break

3:00 pm Session 3: DRAM Issues and Architectures p.105

Session Chair: Robert Voigt, Northrop Grumman

3:00 pm Main Memory Latency Simulation: The Missing Link p.107

Rommel Sanchez Verdejo (Barcelona Supercomputing Center), Kazi Asifuzzaman (Barcelona Supercomputing Center), Milan Radulovic (Barcelona Supercomputing Center), Petar Radojkovic (Barcelona Supercomputing Center), Eduard Ayguade (Barcelona Supercomputing Center), Bruce Jacob (University of Maryland)

3:20 pm Cocoa: Synergistic Cache Compression and Error Correction
in Capacity Sensitive Last Level Caches p.117

Chao Yan (Northwestern University), Russ Joseph (Northwestern University)

3:40 pm Opportunistic Compression for Direct-Mapped DRAM Caches p.129

Alaa Alameldeen (Intel), Rajat Agarwal (Intel)

4:00 pm Tackling Memory Access Latency Through DRAM Row Management p.137

Sriseshan Srikanth (Georgia Institute of Technology), Lavanya Subramanian (Intel Labs), Sreenivas Subramoney (Intel Labs), Thomas Conte (Georgia Institute of Technology), Hong Wang (Intel Labs)

4:20 pm Efficient Coding Scheme for DDR4 Memory Subsystems p.148

Kira Kraft (Technische Universität Kaiserslautern), Deepak M. Mathew (Technische Universität Kaiserslautern), Chirag Sudarshan (Technische Universität Kaiserslautern), Matthias Jung (Fraunhofer), Christian Weis (Technische Universität Kaiserslautern), Norbert Wehn (Technische Universität Kaiserslautern), Florian Longnos (Huawei Technologies Co. Ltd, Data Center Technologies Lab)

4:40 pm Break

5:00 – 7:00 pm Spirited Discussion Maryland Ballroom A

Memory Systems Problems and Solutions

  • Keren Bergman, Columbia University
  • Phil Emma, Systems Technology & Architecture Consulting
  • Adolfy Hoisie, Brookhaven National Lab
  • Rob Ross, Argonne National Lab
  • Jeffrey Vetter, Georgia Tech & Oak Ridge National Lab
  • Ke Zhang, Institute of Computing Technology, Chinese Academy of Sciences

7:30 pm Dinner — Regular attendees: On your own
Program Committee dinner meeting — McCormick & Schmick’s Harborside

Wed Oct 3 Breakfast Maryland Ballroom 1&2 8:00 am

Wednesday Meeting: Maryland Ballroom A

9:00 am Hardware Keynote: Steve Wallach
Founder of Convey, purchased by Micron, now Director of Design-Engineering

10:00 am Break

10:20 am Session 4: Memory for Parallel Systems & Architectures II p.159

Session Chair: Kurt Keville, MIT

10:20 am Linking Parallel Algorithmic Thinking to Many-Core Memory Systems
and Speedups for Boosted Decision Trees p.161

James Edwards (University of Maryland), Uzi Vishkin (University of Maryland)

10:40 am Profile-Guided Scope-Based Data Allocation Method p.169

Hugo Brunie (CEA/DAM Ile de France), Julien Jaeger (CEA/DAM Ile de France), Patrick Carribault (CEA/DAM Ile de France), Denis Barthou (Bordeaux INP)

11:00 am Enhancing High-Level Synthesis of Accelerators for Memory-bound Workloads p.183

Marco Minutoli (Pacific Northwest National Laboratory), Vito Giovanni Castellana (Pacific Northwest National Laboratory), Antonino Tumeo (Pacific Northwest National Laboratory), Nicola Saporetti (Politecnico di Milano), Stefano Devecchi (Politecnico di Milano), Marco Lattuada (Politecnico di Milano), Pietro Fezzardi (Politecnico di Milano), Fabrizio Ferrandi (Politecnico di Milano)

11:20 am Achieving Transparency Mapping Parallel Applications: A Memory Hierarchy Affair p.187

Edgar A Leon (Lawrence Livermore National Laboratory), Matthieu Hautreux (French Alternative Energies and Atomic Energy Commission)

11:40 am Hardware Transactional Persistent Memory p.192

Ellis Giles (Rice University), Kshitij Doshi (Intel), Peter Varman (Rice University)

12:00 pm Conference Awards Luncheon Maryland Ballroom 1&2

1:00 pm Session 5: Modeling and Simulation p.209

Session Chair: Ishwar Bhati, Intel

1:00 pm HMCTherm: A Cycle-accurate HMC Simulator
Integrated with Detailed Power and Thermal Simulation p.211

Zhiyuan Yang (University of Maryland), Michael Zuzak (University of Maryland), Ankur Srivastava (University of Maryland)

1:20 pm Design Space Exploration of Near Memory Accelerators p.220

Scott Lloyd (Lawrence Livermore National Laboratory), Maya Gokhale (Lawrence Livermore National Laboratory)

1:40 pm Fine-Grained Data Usage Analysis by Access Sampling: Seeing the Data
That Is Not There p.223

Zhizhou Zhang (University of California, Santa Barbara), Chencheng Ye (Huazhong University of Science and Technology), Rahman Lavaee (Google), Ning Gu (Rutgers University), Chen Ding (University of Rochester)

2:00 pm Footprint Modeling of Cache Associativity and Granularity p.234

Hao Luo (Google), Guoyang Chen (Alibaba Group), Fangzhou Liu (University of Rochester), Pengcheng Li (Google), Chen Ding (University of Rochester), Xipeng Shen (North Carolina State University)

2:20 pm Data-Driven Spatial Locality p.245

Svetozar Miucin (University of British Columbia), Alexandra Fedorova (University of British Columbia)

2:40 pm Break

3:00 pm Session 6: Exotic Technologies and Applications p.257

Session Chair: Petar Radojkovic, Barcelona Supercomputing Center

3:00 pm Optically Connected and Reconfigurable GPU Architecture
for Optimized Peer-to-Peer Access p.259

Erik Anderson (Columbia University), Jorge Gonzalez (University of Campinas), Alexander Gazman (Columbia University), Rodolfo Azevedo (University of Campinas), Keren Bergman (Columbia University)

3:20 pm Multi-Level Memristive Voltage Divider: Programming Scheme Trade-offs p.261

Tobias Lieske (Friedrich-Alexander-University), Mehrdad Biglari (Friedrich-Alexander University), Dietmar Fey (University Erlangen-Nuremberg)

3:40 pm AWGR-based Optical Processor-to-Memory Communication
for Low-latency, Low-energy Vault Accesses p.271

Sebastian Werner (University of California, Davis), Pouya Fotouhi (University of California, Davis), Roberto Proietti (University of California, Davis), S.J. Ben Yoo (University of California, Davis)

4:00 pm Leveraging MLC STT-RAM for Energy-efficient CNN Training p.281

Hengyu Zhao (University of California San Diego), Jishen Zhao (University of California San Diego)

4:20 pm Memory-System Requirements for Convolutional Neural Networks p.293

Antara Ganguly (Indian Institute of Technology Bombay), Virendra Singh (Indian Institute of Technology Bombay), Rajeev Muralidhar (Intel), Masahiro Fujita (University of Tokyo)

4:40 pm Break

5:00 – 7:00 pm Spirited Discussion Maryland Ballroom A

New and Cool Memory Technologies

  • Shekhar Borkar, Qualcomm
  • Ron Brightwell, Sandia National Labs
  • Wendy Elsasser,  Arm
  • Michael Healy, IBM
  • David Resnick, “in the process of retiring …”
  • Owens Walker, United States Naval Academy

7:30 pm Conference Dinner & Entertainment
Bobby McKeys Dueling Piano Bar
164 Fleet St., National Harbor

Thu Oct 4 Breakfast Annapolis Room 3&4 8:00 am

Thursday Meeting: Annapolis Room 1&2

8:40 am Session 7: Invited Papers p.301

Session Chair: David Donofrio, Berkeley Lab

8:40 am PPT-GPU: Performance Prediction Toolkit for GPUs
(Identifying the impact of caches: Extended Abstract) p.303

Yehia Arafa (New Mexico State University), Abdel-Hameed Badawy (New Mexico State University), Gopinath Chennupati (Los Alamos National Laboratory), Nandakishore Santhi (Los Alamos National Laboratory), Stephan Eidenbenz (Los Alamos National Laboratory)

9:00 am Open2C: Open-source Generator for Coherent Cache Memory Subsystem Exploration p.305

Anastasiia Butko (Lawrence Berkeley National Lab), Albert Chen (University of California, Berkeley), David Donofrio (Lawrence Berkeley National Lab), Farzad Fatollahi-Fard (Lawrence Berkeley National Lab), John Shalf (Lawrence Berkeley National Lab)

9:20 am Demonstration of Superconducting Memory for an RQL CPU p.312

Randall Burnett (Northrop Grumman Corporation), Ryan Clarke (Northrop Grumman Corporation), Tim Lee (Northrop Grumman Corporation), Harold Hearne (Northrop Grumman Corporation), Jacob Vogel (Northrop Grumman Corporation), Quentin Herr (Northrop Grumman Corporation), Anna Herr (Northrop Grumman Corporation)

9:40 am Towards Detection of Modified Firmware on Solid State Drives
via Side Channel Analysis insert

Dane Brown (U.S. Naval Academy), Owens Walker (U.S. Naval Academy), Ryan Rakvic (U.S. Naval Academy), Robert Ives (U.S. Naval Academy), Hau Ngo (U.S. Naval Academy), James Shey (U.S. Naval Academy), Justin Blanco (U.S. Naval Academy)

10:00 am Break

10:20 am Session 8: Experimentations & Optimizations p.315

Session Chair: Zeshan Chishti, Intel

10:20 am Architecting a Hardware-Managed Hybrid DIMM Optimized for Cost/Performance p.317

Fred Ware (Rambus Inc.), Javier Bueno (Metempsy), Liji Gopalakrishnan (Rambus Inc.), Brent Haukness (Rambus Inc.), Chris Haywood (Rambus Inc.), Toni Juan (Metempsy), Eric Linstadt (Rambus Inc.), Sally A. McKee (Clemson University), Steven C. Woo (Rambus Inc.), Kenneth L. Wright (Rambus Inc.), Craig Hampel (Rambus Inc.), Gary Bronner (Rambus Inc.)

10:40 am A Performance & Power Comparison of Modern High-Speed DRAM Architectures p.331

Shang Li (University of Maryland), Dhiraj Reddy (University of Maryland), Bruce Jacob (University of Maryland)

11:00 am A Raspberry Pi Operating System for Exploring Advanced Memory System Concepts p.344

Pascal Francis-Mezger (University of Maine), Vincent Weaver (University of Maine)

11:20 am Stake: A Coupled Simulation Environment for RISC-V Memory Experiments p.355

John Leidel (Tactical Computing Laboratories)

11:40 am Driving into the Memory Wall: The Role of Memory
for Advanced Driver Assistance Systems and Autonomous Driving p.367

Matthias Jung (Fraunhofer), Sally A. McKee (Clemson University), Chirag Sudarshan (Technische Universität Kaiserslautern), Christoph Dropmann (Fraunhofer), Christian Weis (Technische Universität Kaiserslautern), Norbert Wehn (Technische Universität Kaiserslautern)

12:00 pm Postamble: J. Thomas Pawlowski
Chief Technologist / Micron Fellow
Architecture Development, Micron

12:40 pm Closing Remarks