Conference Organizers

  • Bruce Jacob, U. Maryland
  • Kathy Smiley, Memory Systems
  • Ameen Akel, Micron
  • James Ang, Sandia
  • Ishwar Bhati, Oracle
  • Angelos Bilas, FORTH
  • Mu-Tien Chang, Samsung
  • Zeshan Chishti, Intel
  • Skevos Evripidou, U. Cyprus
  • Brinda Ganesh, Intel
  • Georgi Gaydadjiev, Maxeler
  • James Goodman, U. Auckland
  • Hillery Hunter, IBM
  • Bharath Iyer, Samsung
  • Aamer Jaleel, NVIDIA
  • David Kaeli, Northeastern
  • Dean Klein, Micron
  • Hsien-Hsin Lee, TSMC
  • Gabriel Loh, AMD
  • Shih-Lien Lu, Intel
  • Sally McKee, Chalmers
  • Avi Mendelson, Technion
  • Trevor Mudge, U. Michigan
  • Richard Murphy, Micron
  • David Resnick, Sandia
  • Scott Rixner, Rice
  • Arun Rodrigues, Sandia
  • Kevin Skadron, U. Virginia
  • Sadagopan Srinivasan, AMD
  • Pedro Trancoso, U. Cyprus
  • Ankush Varma, Intel
  • Robert Voigt, Northrop Grumman
  • David Wang, Inphi

Conference Schedule

Mon Oct 5

Welcome Reception 5:00 pm

Tue Oct 6

7:30 am Breakfast in the Hotel Restaurant

8:40 am Opening Remarks

9:00 am Keynote: J. Thomas Pawlowski, Micron

Chief Technologist / Micron Fellow

Architecture Development

10:00 am Break

10:20 am Session 1: Opportunities and Challenges

Session Chair: Hillery Hunter, IBM

10:20 am Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems

Gabriel H. Loh (Advanced Micro Devices), Natalie Enright Jerger (Advanced Micro Devices and University of Toronto), Ajaykumar Kannan (University of Toronto), Yasuko Eckert (Advanced Micro Devices)

10:40 am Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore

Syed Minhaj Hassan (Georgia Institute of Technology), Sudhakar Yalamanchili (Georgia Institute of Technology), Saibal Mukhopadhyay (Georgia Institute of Technology)

11:00 am Opportunities and Challenges of Performing Vector Operations
inside the DRAM

Marco A. Z. Alves (Federal University of Rio Grande do Sul), Paulo C. Santos (Federal University of Rio Grande do Sul), Matthias Diener (Federal University of Rio Grande do Sul), Luigi Carro (Federal University of Rio Grande do Sul)

11:20 am SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype

Chad D. Kersey (Georgia Institute of Technology), Sudhakar Yalamanchili (Georgia Institute of Technology), Hyesoon Kim (Georgia Institute of Technology)

11:40 am Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?

Milan Radulovic (Barcelona Supercomputing Center & Universitat Politècnica de Catalunya), Darko Zivanovic (Barcelona Supercomputing Center & Universitat Politècnica de Catalunya), Daniel Ruiz (Barcelona Supercomputing Center), Bronis R. de Supinski (Lawrence Livermore National Lab), Sally A. McKee (Chalmers University of Technology), Petar Radojkovic (Barcelona Supercomputing Center), Eduard Ayguade (Barcelona Supercomputing Center)

12:00 pm Conference Lunch

1:00 pm Session 2: Rethinking Architectures and Design Approaches

Session Chair: Zeshan Chishti, Intel

1:00 pm A Data Centric Perspective on Memory Placement

Yitzhak Birk (Technion), Oskar Mencer (Maxeler Technologies)

1:20 pm The Semantic Gap Between Software and the Memory System p.43

Jim Stevens (University of Maryland), Paul Tschirhart (University of Maryland), Bruce Jacob (University of Maryland)

1:40 pm MMC: a Many-core Memory Connection Model

Chen Ding (University of Rochester), Hao Lu (University of Rochester), Chencheng Ye (University of Rochester)

 2:00 pm High Performance Computing Co-Design Strategies p.51

James A. Ang (Sandia National Laboratories)

2:20 pm Break

2:40 pm Session 3: The Devil is in the Details

Session Chair: Dave Wang, Inphi

2:40 pm Opportunities to Upgrade Main Memory

Dave Resnick (Sandia National Laboratories)

3:00 pm E-ECC: Low Power Erasure and Error Correction Schemes for Increasing Reliability of Commodity DRAM Systems

HsingMin Chen (Arizona State University), Akhil Arunkumar (Arizona State University), CaroleJean Wu (Arizona State University), Trevor Mudge (University of Michigan), Chaitali Chakrabarti (Arizona State University)

3:20 pm Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design

Ali Eslami (Duke University), Alfredo Velasco (Duke University), Alireza Vahid (Duke University), Georgios Mappouras (Duke University), Robert Calderbank (Duke University), Daniel Sorin (Duke University)

3:40 pm Achieving Yield, Density and Performance Effective DRAM at Extreme Technology Sizes

Bruce R. Childers (University of Pittsburgh), Jun Yang (University of Pittsburgh), Youtao Zhang (University of Pittsburgh)

4:00 pm Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs

Matthias Jung (University of Kaiserslautern), Éder Zulian (University of Kaiserslautern), Deepak M. Mathew (University of Kaiserslautern), Matthias Herrmann (University of Kaiserslautern), Christian Brugger (University of Kaiserslautern), Christian Weis (University of Kaiserslautern), Norbert Wehn (University of Kaiserslautern)

4:20 pm Break

5:00 pm Discussion 5:00 pm

Memory Systems Problems and Solutions

  • Hillery Hunter, IBM
  • Mike Ignatowski, AMD
  • Aamer Jaleel, NVIDIA
  • Dave Resnick, Sandia
  • Dave Wang, Inphi

7:00 pm Dinner — on your own

Wed Oct 7

7:30 am Breakfast in the Hotel Restaurant

8:40 am Invited Session

Memory as an Enabling Technology for Exascale Systems — DOE and NSA Perspectives

  • Thuc Hoang, NNSA
  • Thomas Salter, ACS (talk given by Noel Wheeler)
  • TBD

10:00 am Break

10:20 am Session 4: Caches and Software Management of Memory

Session Chair: MuTien Chang, Samsung

10:20 am Implications of Memory Interference for Composed HPC Applications

Brian Kocoloski (University of Pittsburgh), Yuyu Zhou (University of Pittsburgh), Bruce Childers (University of Pittsburgh), John Lange (University of Pittsburgh)

10:40 am Software Techniques for Scratchpad Memory Management

Paul Sebexen (REX Computing), Thomas Sohmers (REX Computing)

11:00 am Dynamic Memory Pressure Aware Ballooning

Jinchun Kim (Texas A&M University), Viacheslav Fedorov (Texas A&M University), Paul V. Gratz (Texas A&M University), A.L. Narasimha Reddy (Texas A&M University)

11:20 am Shared Last-Level Caches and the Case for Longer Timeslices

Viacheslav V. Fedorov (Texas A&M University), A. L. Narasimha Reddy (Texas A&M University), Paul V. Gratz (Texas A&M University)

11:40 am S-L1: A Software-based GPU L1 Cache that Outperforms the Hardware L1 for Data Processing Applications

Reza Mokhtari (University of Toronto), Michael Stumm (University of Toronto)

12:00 pm Conference Lunch

1:00 pm Session 5: Design and Simulation Methodologies

Session Chair: Robert Voigt, Northrop Grumman

1:00 pm Architecture Exploration for Data Intensive Applications

Fernando Martin del Campo (University of Toronto), Paul Chow (University of Toronto)

1:20 pm MEMST: Cloning Memory Behavior Using Stochastic Traces

Ganesh Balakrishnan (Advanced Micro Devices), Yan Solihin (North Carolina State University)

1:40 pm Modeling Data Movement in the Memory Hierarchy in HPC Systems

Aditya M. Deshpande (Information Sciences Institute, University of Southern California), Jeffrey T. Draper (Information Sciences Institute, University of Southern California)

2:00 pm Rethinking Design Metrics for Datacenter DRAM

Manu Awasthi (Samsung Semiconductor)

2:20 pm Break

2:40 pm Session 6: Multi-Level and Hybrid Main Memories

Session Chair: Aamer Jaleel, NVIDIA

2:40 pm HpMC: An Energy-aware Management System of Multi-level Memory Architectures

ChunYi Su (Virginia Tech), Edgar A. Leon (Lawrence Livermore National Laboratory), Gabriel Loh (Advanced Micro Devices), David Roberts (Advanced Micro Devices), Kirk W. Cameron (Virginia Tech), Dimitrios S. Nikolopoulos (Queen’s University of Belfast), Bronis R. de Supinski (Lawrence Livermore National Laboratory)

3:00 pm Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance

Paul Tschirhart (University of Maryland), Jim Stevens (University of Maryland), Zeshan Chishti (Intel Labs), ShihLien Lu (Intel Labs), Bruce Jacob (University of Maryland)

3:20 pm The Potential and Perils of Multi-Level Memory

Jagan Jayaraj (Sandia National Laboratories), Arun Rodrigues (Sandia National Laboratories), Simon Hammond (Sandia National Laboratories), Gwendolyn Voskuilen (Sandia National Laboratories)

3:40 pm k-Means Clustering on Two-Level Memory Systems

Michael A. Bender (Stony Brook University), Jonathan Berry (Sandia National Laboratories), Simon D. Hammond (Sandia National Laboratories), Branden Moore (Sandia National Laboratories), Benjamin Moseley (Washington University), Cynthia A. Phillips (Sandia National Laboratories)

4:00 pm Towards Workload-Aware Page Cache Replacement Policies for Hybrid Memories

Ahsen J. Uppal (The George Washington University), Mitesh R. Meswani (Advanced Micro Devices)

4:20 pm Break

5:00 pm Spirited Discussion

New and Cool Memory Technologies (e.g., HBM and HMC)

  • Wendy Elsasser, ARM
  • Jaejin Lee, SK Hynix
  • Gabriel Loh, AMD
  • Mike O’Connor, NVIDIA
  • Thomas Pawlowski, Micron

7:00 pm Conference Dinner & Awards Ceremony

Thu Oct 8

7:30 am Breakfast in the Hotel Restaurant

8:40 am Session 7: A Focus on Applications

Session Chair: Arun Rodrigues, Sandia

8:40 am Anatomy of GPU Memory System for Multi-Application Execution

Adwait Jog (College of William and Mary), Onur Kayiran (Advanced Micro Devices), Tuba Kesten (The Pennsylvania State University), Ashutosh Pattnaik (The Pennsylvania State University), Evgeny Bolotin (NVIDIA), Niladrish Chatterjee (NVIDIA), Stephen W. Keckler (NVIDIA and UT Austin), Mahmut T. Kandemir (The Pennsylvania State University), Chita R. Das (The Pennsylvania State University)

9:00 am Inefficiencies in the Cache Hierarchy: A Sensitivity Study of Cacheline Size with Mobile Workloads

Anouk Van Laer (University College London), William Wang (ARM Research), Chris Emmons (ARM Research)

9:20 am Herniated Hash Tables: Exploiting Multi-Level Phase Change Memory for In-Place Data Expansion

Zhaoxia Deng (University of California, Santa Barbara), Lunkai Zhang (University of California, Santa Barbara), Diana Franklin (University of California, Santa Barbara), Frederic T. Chong (University of California, Santa Barbara)

9:40 am Instruction Offloading with HMC 2.0 Standard — a Case Study for Graph Traversals

Lifeng Nai (Georgia Institute of Technology), Hyesoon Kim (Georgia Institute of Technology)

10:00 am Break

10:20 am Session 8: Systems and Techniques for In-Memory Processing

Session Chair: Ameen Akel, Micron

10:20 am Energy Efficient Scale-In Clusters with In-Storage Processing for Big-Data Analytics

  1. Stephen Choi (Samsung Semiconductor), YangSuk Kee (Samsung Semiconductor)

10:40 am NCAM: Near-Data Processing for Nearest Neighbor Search

Carlo C. del Mundo (University of Washington), Vincent T. Lee (University of Washington), Luis Ceze (University of Washington), Mark Oskin (University of Washington)

11:00 am Understanding Energy Aspect of Processing Near Memory for HPC Workloads

Hyojong Kim (Georgia Institute of Technology), Hyesoon Kim (Georgia Institute of Technology), Sudhakar Yalamanchili (Georgia Institute of Technology), Arun Rodrigues (Sandia National Laboratories)

11:20 am Near Memory Data Structure Rearrangement

Maya Gokhale (Lawrence Livermore National Lab), Scott Lloyd (Lawrence Livermore National Lab), Chris Hajas (University of Florida)

11:40 am Closing Remarks