Bruce Jacob, General Chair

Welcome to the Sixth International Symposium on Memory Systems, held virtually due to travel restrictions being in place [2020 has been a crazy year!]. Thank you so much for submitting your work; we think we have a very interesting program planned for you, one which could not have happened without your research, your insights, and your hard work. 

As we mentioned in the original Call for Papers, in the last few decades the memory system has become extremely important. Memory is slow, and this is the primary reason that computers don’t run significantly faster than they do. In large-scale computer installations such as the building-sized systems powering,, and the financial sector, memory is often the largest dollar cost as well as the largest dissipator of power and consumer of energy. Consequently, improvements in the memory system can have significant impact on the real world, improving power and energy, performance, and/or dollar cost. Several emerging technologies promise to make improvements in all of these dimensions, but they are still not widely understood and not well characterized. Lastly, many of the problems we see in the memory system are cross-disciplinary in nature — their solution would likely require work at all levels, from applications to circuits.

Thus, our primary goal with this conference is to showcase interesting ideas that would spark conversation between disparate groups — to get applications people and operating systems people and compiler people and system architecture people and interconnect people and circuits people to talk to each other about the larger problem. We believe that the first step has been taken successfully: the technical program contains plenty of material for you to discuss. The rest is completely in your hands: you, the participants, represent a wide diversity of disciplines within the field of computer design, and the true success of this conference will be measured by the degree to which you interact with each other and discuss the field’s many problems and potential solutions. Please help make this conference a fruitful experience for all, by participating in discussions and providing your insights. 

Thank you again for participating. I look forward to seeing your presentations!

Bruce Jacob, University of Maryland


Bruce Jacob, University of Maryland
Kathy Smiley, Memory Systems
Yitzhak Birk, Technion
Chen Ding, University of Rochester
Dave Dunning, Qualcomm
Matthias Jung, Fraunhofer IESE
John Leidel, Tactical Computing Labs
Petar Radojkovic, BSC
Arun Rodrigues, Sandia National Labs
Kevin Rudd, DoD
Robert Trout, Micron
Ameen Akel, Micron
James Ang, PNNL
Abdel-Hameed Badawy, NMSU
Jonathan Beard, Arm
Bruce Childers, University of Pittsburgh
Zeshan Chishti, Intel
Bruce Christenson, Intel
David Donofrio, Tactical Computing Labs
Wendy Elsasser, Arm
Dietmar Fey, FAU Erlangen-Nürnberg
Maya Gokhale, LLNL
Michael Healy, IBM
Thuc Hoang, NNSA
Mike Ignatowski, AMD
Michael Jantz, University of Tennessee
Hyesoon Kim, Georgia Tech
Edgar Leon, LLNL
Scott Lloyd, LLNL
Trevor Mudge, University of Michigan
J. Thomas Pawlowski, Pawlowski Cons.
Hemant Rotithor, Arm
Robert Voigt, Northrop Grumman
Gwendolyn Voskuilen, Sandia National Labs
Owens Walker, US Naval Academy
David Wang, Samsung
Norbert Wehn, U. Kaiserslautern
Noel Wheeler, DoD

Conference Programme:

Runtime Estimation of Application Memory Latency for Performance Analysis and Optimization
Huanxing Shen, Cong Li
SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge
Irina Alam, Puneet Gupta
Paper, Video
Near-memory & In-Memory Detection of Fileless Malware
Marcus Botacin, Andre Gregio, Marco A. Z. Alves
Paper, Video
Parallel HashTable Design for NDP Systems
Pranith Kumar, Hyesoon Kim
Paper, Video
ExPress: Simultaneously Achieving Storage, Performance and Energy Efficiencies in Sparse Matrix Computations
Shashank Adavally, Nagendra Gulur, Krishna Kavi, Alex Weaver, Pranoy Dutta, Benjamin Wang
Paper, Video
Decentralized Offload-based Execution on Memory-centric Compute Cores
Saambhavi Baskaran, Jack Sampson
Paper, Video
Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine
Wonbo Shim, Hongwu Jiang, Xiaochen Peng, Shimeng Yu
Paper, Video
Analysis of the Usage Models of System Memory Management Unit in Accelerator-attached Translation Units
Kyriakos Paraskevas, Konstantinos Iordanou, Mikel Luján, John Goodacre
Paper, Video
DELTA: Validate GPU Memory Profiling with Microbenchmarks
Xianwei Zhang, Evgeny Shcherbakov
Paper, Video
Towards Automating Application-Specific Address Mapping for Emerging Memory Devices
Shashank Adavally, Vignesh Adhinarayanan, Krishna Kavi
Paper, Video
An Energy Efficient 3D-Heterogeneous Main Memory Architecture for Mobile Devices
Deepak M. Mathew, Felipe S. Prado, Éder F. Zulian, Christian Weis, Muhammad Mohsin Ghaffar, Matthias Jung, Norbert Wehn
Paper, Video
Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory
Sven Müelich, Chirag Sudarshan, Christian Weis, Martin Bossert, Robert F.H. Fischer, Norbert Wehn
Paper, Video
The case for optimizing the frequency of periodic data movements over hybrid memory systems
Thaleia Dimitra Doudali, Daniel Zahka, Ada Gavrilovska
Paper, Video
CircusTent: A Benchmark Suite for Atomic Memory Operations
Brody Williams, John Leidel, Xi Wang, David Donofrio, Yong Chen
Paper, Video
An In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions
Muhammad Mohsin Ghaffar, Chirag Sudarshan, Christian Weis, Matthias Jung, Norbert Wehn
Paper, Video
The Need for Precise and Efficient Memory Capacity Budgeting
Shaleen Garg, Sudarsun Kannan, Manish Parashar
Paper, Video
X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer Architectures
Sven Rheindt, Temur Sabirov, Oliver Lenke, Thomas Wild, Andreas Herkersdorf
Paper, Video
Efficient Orchestration of Host and Remote Shared Memory for Memory Intensive Workloads.
Juhyun Bae, Ling Liu, Gong Su, Arun Iyengar, Yanzhao Wu
Paper, Video
Evaluating Gather Scatter Performance on CPUs and GPUs
Patrick Lavin, Jason Riedy, Jeffrey Young, Richard Vuduc, Aaron Vose, Daniel Ernst
Paper, Video
Performance Modeling and Evaluation of a Production Disaggregated Memory System
Xian-He Sun, Ning Zhang, Brian Toonen, Bill Allcock
Paper, Video
Efficient Generation of Application Specific Memory Controllers
Marco V. Natale, Matthias Jung, Kira Kraft, Frederik Lauer, Johannes Feldmann, Chirag Sudarshan, Christian Weis, Sven Krumke, Norbert Wehn
Paper, Video
Bucket-Based Expiration Algorithm: Improving Eviction Efficiency for In-Memory Key-Value Database
Guochao Xie, Yeh-Ching Chung
Paper, Video
ObfusGEM: Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design
Michael Zuzak, Ankur Srivastava
Paper, Video
Dynamically Configuring LRU Replacement Policy in Redis
Yuchen Wang, Junyao Yang, Zhenlin Wang
Paper, Video
CLAM: Compiler Lease of Cache Memory
Ian Prechtl, Ben Reber, Chen Ding, Dorin Patru, Dong Chen
Paper, Video
Things to Consider to Enable Dynamic Graphs in Processing-in-Memory
Euna Kim, Hyesoon Kim
Paper, Video
WAL-assisted Tiering: Painlessly Improving Your Favorite Log-Structured KV Store Instead of Building a New One
Xubin Chen, Jingpeng Hao, Yifan Qiao, Tong Zhang
Paper, Video
Improving Memory Reliability by Bounding DRAM Faults:  DDR5 improved reliability features
Kjersten Criss, Kuljit Bains, Rajat Agarwal
Paper, Video
PreFAM: Understanding the Impact of Prefetching inFabric-Attached Memory Architectures
Vamsee Reddy Kommareddy, Jagadish Kotra, Clayton Hughes, Simon David Hammond, Amro Awad
Paper, Video
Neural Network Weight Compression with NNW-BDI
Andrei Bersatti, Nima Shoghi Ghalehshahi, Hyesoon Kim
Paper, Video
PPT-SASMM: Scalable Analytical Shared Memory Model
Atanu Barai, Gopinath Chennupati, Nandakishore Santhi, Abdel-Hameed Badawy, Yehia Arafa, Stephan Eidenbenz
Paper, Video
RAOP: Recurrent Neural Network Augmented Offset Prefetcher
Pengmiao Zhang, Ajitesh Srivastava, Benjamin Brooks, Rajgopal Kannan, Viktor K. Prasanna
Paper, Video