Papers:
| Title: | Authors: | Paper/Video | Video |
|---|---|---|---|
| Evaluating HPC Kernels for Processing in Memory | Kazi Asifuzzaman, Mohammad Alaul Haque Monil, Frank Liu, Jeffrey S. Vetter | Paper | |
| Dynamic Page Policy Using Perceptron Learning | Muhammad Rafique, Zhichun Zhu | Paper | No Video |
| A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices | Kaustav Goswami, Shirshendu Das, Sagar Satapathy, Dip Sankar Banerjee | Paper | |
| Using Many Small 1T1C Memory Arrays in a Large and Dense Multicore Processor | Gunnar Carlstedt, Mats Rimborg | Paper | |
| A Framework for Formal Verification of DRAM Controllers | Lukas Steiner, Chirag Sudarshan, Matthias Jung, Dominik Stoffel, Norbert Wehn | Paper | |
| Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly | Samiksha Verma, Shirshendu Das | Paper | |
| FPGA-accelerated simulation of variable latency memory systems | Husrev Cilasun, Chris Macaraeg, Ivy Peng, Abhik Sarkar, Maya Gokhale | Paper | |
| Unveiling the Real Performance of LPDDR5 Memories | Lukas Steiner, Matthias Jung, Michael Huonker, Norbert Wehn | Paper | |
| Cronus: Computer Vision-based Machine Intelligent Hybrid Memory Management | Thaleia Dimitra Doudali, Ada Gavrilovska | Paper | |
| Exploiting Data Source Distribution to Enhance NVM Reliability | Amit Berman | Paper | |
| Position Paper: Toward Classification of Phase Change Memory and 3D NAND Flash SSDs Using Power-based Side-channel Analysis in the Time-domain | Jennie Hill, Justin Blanco, James Shey, Ryan Rakvic, Owens Walker | Paper | |
| In-memory Bulk Bitwise Logic Operation for Multi-level Cell Non-volatile Memories | Sayed Ahmad Salehi | Paper |